December 2003 - cypherpunks-legacy

ALA/ACLU file lawsuit challenging NY "CDA" law, from NNN
by Declan McCullagh 17 Dec '03

17 Dec '03

---------- Forwarded message ---------- Date: Tue, 14 Jan 1997 08:43:52 -0800 (PST) From: Declan McCullagh <declan(a)well.com> To: fight-censorship(a)vorlon.mit.edu Subject: ALA/ACLU file lawsuit challenging New York "CDA" law [Visit netlynews.com for the rest of the story. Another reason to follow the New York case is that a successful challenge to its "harmful to minors" ban could create a useful precedent in fighting a CDA 2.0, which likely will have such language. --Declan] *********** The Netly News Network http://netlynews.com A Civil (Libertarian) War by Declan McCullagh (declan(a)well.com) January 14, 1997 On a frosty winter morning last February, Shabbir Safdar and a gaggle of VTW loyalists trekked to Albany, New York, to protest a state bill that would muzzle the Net. "This was our first time doing any state-level lobbying," Safdar says. "We managed to convince them to take some stuff out of the law." But his efforts didn't stop the measure from wending its way through the legislature: In September, Governor George Pataki signed it into law. Today the ACLU sued New York State in federal court, charging that the law is unconstitutional. New York now takes its place among two dozen states battling similar local legislation that would criminalize certain forms of Net speech. In Georgia, for instance, merely having an anonymous user name could be illegal. Virginia restricts state employees' rights to view sexually explicit material -- college professors who might want to use the Net in, say, an English lit class have to exercise extreme caution. Forget the Communications Decency Act: A kind of civil war is being waged across half the U.S. The ALA v. Pataki lawsuit, filed in the Southern District of New York, involves 14 plaintiffs including the American Library Association, the American Booksellers Association Foundation for Free Expression, Panix, Echo and the ACLU. The coalition, which is asking for a permanent injunction, maintains that the law unconstitutionally stifles online speech and unduly interferes with interstate commerce. The law amends the penal code by making it a criminal offense punishable by seven years in prison to distribute pictures or text "which (are) harmful to minors." We here at The Netly News are ardent advocates of free speech, of course -- we held a joint teach-in on the New York law in the fall. So I spoke to Ann Beeson, a staff attorney at the ACLU, who's spent the last year attacking other state laws and the CDA in court. Why should netizens care about this law if they don't live in New York? I asked her. "Because New York can extradite you," she replied. But what if it's not a crime where I live? "It doesn't make a difference," Beeson said. "There's no question that New York could try to extradite you if you put up a web site that has material harmful to minors on it." [...]

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Re: RSA challenge: is it legal to try?
by Greg Broiles 17 Dec '03

17 Dec '03

At 01:50 PM 1/13/97 -0800, Ian Goldberg wrote: >According to http://www.rsa.com/rsalabs/newfaq/q76.html, RSA is in the >process of patent application for RC5. Does that mean it's illegal to >write a keysearch program for the RC5 challenges (unless you use BSAFE >or something like that)? Seems to me that a defendant who was participating in the challenge (or working with people who were, or was getting ready to participate) would have a strong argument that RSA gave implicit permission to use the patented algorithm in connection with the contest, or that a patent infringement action by RSA against a defendant who was participating in the contest would be barred by the doctrine of equitable estoppel. (Very broadly, equitable estoppel says that you can't tell someone "X", and then sue them on a theory of "not X", or come to court and argue that they are liable because of "not X".) Perhaps somewhere in the contest rules there's a limitation on the software/source code to be used? (I poked through the contest stuff a few days ago, and didn't see anything like that, but I got the impression that they weren't entirely finished putting it together.) YMMV, IANALUIPTB (.. until I pass the bar), etc. But it would be monumentally stupid to create a contest and then punish people for participating. The contest seems likely to do two things (beyond test the strength of the algorithm): develop an installed multiplatform base of optimized code which runs RC5, and give people who possess/distribute it a legal reason for having done so. So it'll be tough to stuff the RC5 rabbit back in the hat when the contest is over. RC5 seems destined to end up like RSA public-key, Diffie-Hellman, and IDEA - publically available (and probably deployed in free "rogue" software) yet only available commercially for a fee. Presumably the RC5 patent (if one is awarded) won't suffer from the peculiarities of the international patent schemes which made RSA only patentable in the US. -- Greg Broiles | US crypto export control policy in a nutshell: gbroiles(a)netbox.com | http://www.io.com/~gbroiles | Export jobs, not crypto. |

1 0

Checking debit
by geo2＠usa.net 17 Dec '03

17 Dec '03

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4 3

Re: RSA
by mixmaster＠remail.obscura.com 17 Dec '03

17 Dec '03

Timmy May likes to lick the semen-shit mixture that accumulates in the crack of his mother's ass. __ /_/\__ \_\/\_\ Timmy May /\_\/_/ \/_/

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Re: New US regs ban downloadable data-security software
by Ian Goldberg 17 Dec '03

17 Dec '03

Lucky Green said: > The new US crypto export regulations control the export of most if not all > data-security software. Regardless if the software uses cryptography or > not. Many software archives seem to be in violation of the new regs. > > <snip> > > This certainly controls virus checkers, firewalls, and other security > software. There are substantial penalties involved in violating the EAR. > The US can assess daily penalties and block all exports of a company's > non-violating products. Criminal penalties apply as well. > > "Export", as defined in the new regs, includes making software available on > the web or via ftp. After _very_ careful reading of the Export Administration Regulations (EAR) (though IANAL), it would seem that the above is slightly inaccurate. Although, as Lucky pointed out, virus checkers et al. are indeed regulated for export from the US, and putting software up for ftp or WWW is considered export, the EAR does _not_ apply to "publicly available" software (732.2(b)(1)). Software is publicly available "when it is available for general distribution either for free or at a price that does not exceed the cost of reproduction and distribution" (734.7(b)). Therefore, it would seem that, as long as the security software on your ftp or WWW site is free of cost, it is OK to keep it there. Commercial security software, however, remains export-restricted. NOTE, however, that products that actually do contain cryptography fall under an exception (734.7(c)): "Notwithstanding paragraphs (a) and (b) of this section, note that encryption software controlled under ECCN 5D002 for ``EI'' reasons on the Commerce Control List (refer to Supplement No. 1 to part 774 of the EAR) remains subject to the EAR even when publicly available." The software controlled for EI reasons under 5D002 are described as: "EI controls apply to encryption software transferred from the U.S. Munitions List to the Commerce Control List consistent with E.O. 13026 of November 15, 1996 (61 FR 58767) and pursuant to the Presidential Memorandum of that date. Refer to Sec. 742.15 of the EAR." As virus checkers et al. were not on the Munitions List, they are not controlled for EI (Encryption Items) reasons, but rather for NS (National Security) and AT (Anti-Terrorism) reasons. The RISKS: the government suddenly creating (and putting into effect) new rules covering large amounts of software, without warning or (in my opinion) justification. - Ian "again, IANAL"

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Pentium optimizations for DES (BIG)
by geeman＠best.com 17 Dec '03

17 Dec '03

Here is some output of the static code analysis from Intel VTUNE of the win32.??? des crypt routine from LIBDES 4.0 You'll have to fiddle with your text margins to get it looking right. Shown are the U and V pipes, clocks, and penalties for: * unpairable instructs (PU_Inst), * instructs dependent on previous results (Exp_Flow_Dep_???) * addresses dependent on previous instructs (Exp_AGI_???) and the %total time at the instruction, etc. based on a run of "speed.c" sampled at .25 millisec intervals A lot of the penalties are the "AGI" flavor, or "address generation interlock" as in: mov bl, dl 1 mov cl, dh xor esi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 << penalty which **maybe** can be avoided by moving (in this example) the "mov bl,dl" to the earliest possible location where the algorithm semantics are unchanged. But you have to be careful not to kill some other pairing if you do. If I had more time I'd do it! ;) But I wonder if this isn't getting close to the point of diminishing returns ..... the overall stats for the encrypt routine showed about 85% pairing, and averaged out to just slightly less than 1 clock/instruction. Just fyi, the total thruput on my system, a cyrix586 133, was just over 1M encrypts/sec, CBC. ---------------------------------------------------------------------- Address Label Time Instructions Clocks Penalties and Warnings Pairing Issues W 0x103c des_encrypt: 0.17% push ebp 1 Label V 0x103d 0.04% push ebx U 0x103e 0.05% push esi 1 V 0x103f 0.06% push edi U 0x1040 0.04% mov eax, DWORD PTR [esp+20] 1 W * 0x1044 0.11% mov esi, DWORD PTR [eax] 2 Exp_AGI_U_Pen:1 Exp_AGI V 0x1046 0.07% mov edi, DWORD PTR [eax+4] U 0x1049 0.04% mov eax, edi 1 N 0x104b 0.07% shr eax, 4 1 PU_Inst, Exp_Flow_Dep_eax, Exp_Output_Dep_eax N 0x104e 0.11% xor eax, esi 1 Exp_Flow_Dep_eax, Exp_Output_Dep_eax N 0x1050 0.05% and eax, 0f0f0f0fh 1 Exp_Flow_Dep_eax, Exp_Output_Dep_eax N 0x1055 0.05% xor esi, eax 1 Exp_Flow_Dep_eax N 0x1057 0.05% shl eax, 4 1 PU_Inst W 0x105a 0.12% xor edi, eax 1 Exp_Flow_Dep_eax V 0x105c 0.06% mov eax, esi U 0x105e 0.06% shr eax, 16 1 N 0x1061 0.10% xor eax, edi 1 Exp_Flow_Dep_eax, Exp_Output_Dep_eax N 0x1063 0.05% and eax, 0ffffh 1 Exp_Flow_Dep_eax, Exp_Output_Dep_eax N 0x1068 0.06% xor edi, eax 1 Exp_Flow_Dep_eax N 0x106a 0.06% shl eax, 16 1 PU_Inst W 0x106d 0.11% xor esi, eax 1 Exp_Flow_Dep_eax V 0x106f 0.05% mov eax, edi U 0x1071 0.06% shr eax, 2 1 N 0x1074 0.10% xor eax, esi 1 Exp_Flow_Dep_eax, Exp_Output_Dep_eax N 0x1076 0.06% and eax, 033333333h 1 Exp_Flow_Dep_eax, Exp_Output_Dep_eax N 0x107b 0.07% xor esi, eax 1 Exp_Flow_Dep_eax N 0x107d 0.04% shl eax, 2 1 PU_Inst W 0x1080 0.13% xor edi, eax 1 Exp_Flow_Dep_eax V 0x1082 0.06% mov eax, esi U 0x1084 0.04% shr eax, 8 1 N 0x1087 0.11% xor eax, edi 1 Exp_Flow_Dep_eax, Exp_Output_Dep_eax N 0x1089 0.06% and eax, 0ff00ffh 1 Exp_Flow_Dep_eax, Exp_Output_Dep_eax N 0x108e 0.06% xor edi, eax 1 Exp_Flow_Dep_eax N 0x1090 0.07% shl eax, 8 1 PU_Inst W 0x1093 0.12% xor esi, eax 1 Exp_Flow_Dep_eax V 0x1095 0.04% mov eax, edi U 0x1097 0.05% shr eax, 1 1 N 0x1099 0.15% xor eax, esi 1 Exp_Flow_Dep_eax, Exp_Output_Dep_eax N 0x109b 0.05% and eax, 055555555h 1 Exp_Flow_Dep_eax, Exp_Output_Dep_eax N 0x10a0 0.07% xor esi, eax 1 Exp_Flow_Dep_eax N 0x10a2 0.07% shl eax, 1 1 PU_Inst N 0x10a4 0.16% xor edi, eax 1 Exp_Flow_Dep_eax N 0x10a6 0.06% rol esi, 3 1 PU_Inst W 0x10a9 0.11% rol edi, 3 1 PU_Inst V 0x10ac 0.13% xor ebx, ebx U 0x10ae 0.05% mov eax, DWORD PTR [esp+28] 1 V 0x10b2 0.06% xor ecx, ecx U 0x10b4 0.04% cmp eax, 0 1 V 0x10b7 0.06% mov ebp, DWORD PTR [esp+24] U 0x10bb 0.09% je des_encrypt+68a (16c6h) 1 W 0x10c1 des_encrypt+85: 0.06% mov edx, DWORD PTR [ebp+4] 1 Basic_Block, Prev_PV/NP V 0x10c4 0.07% mov eax, DWORD PTR [ebp] U 0x10c7 0.05% xor edx, esi 1 V 0x10c9 0.06% xor eax, esi U 0x10cb 0.05% ror edx, 4 1 V 0x10ce 0.11% and eax, -03030304h U 0x10d3 0.06% and edx, -03030304h 1 V 0x10d9 0.05% mov bl, al U 0x10db 0.08% mov cl, ah 1 V * 0x10dd 0.14% xor edi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x10e3 0.10% shr eax, 16 1 V * 0x10e6 0.10% xor edi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x10ec 0.10% mov bl, al 1 V 0x10ee 0.06% mov cl, ah U * 0x10f0 0.16% xor edi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x10f6 0.11% mov eax, DWORD PTR [ecx+041a6a8h] U 0x10fc 0.08% mov bl, dl 1 V 0x10fe 0.04% mov cl, dh U * 0x1100 0.18% xor edi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x1106 0.11% shr edx, 16 1 PU_Inst V 0x1109 0.13% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x110f 0.11% mov bl, dl 1 V 0x1111 0.06% mov cl, dh U * 0x1113 0.16% xor edi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x1119 0.11% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x111f 0.09% xor edi, eax 1 V 0x1121 0.05% mov edx, DWORD PTR [ebp+12] U 0x1124 0.07% mov eax, DWORD PTR [ebp+8] 1 V 0x1127 0.05% xor edx, edi U 0x1129 0.05% xor eax, edi 1 W 0x112b 0.06% ror edx, 4 1 PU_Inst V 0x112e 0.11% and eax, -03030304h U 0x1133 0.06% and edx, -03030304h 1 V 0x1139 0.05% mov bl, al U 0x113b 0.07% mov cl, ah 1 V * 0x113d 0.17% xor esi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x1143 0.11% shr eax, 16 1 V * 0x1146 0.13% xor esi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x114c 0.11% mov bl, al 1 V 0x114e 0.05% mov cl, ah U * 0x1150 0.17% xor esi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x1156 0.11% mov eax, DWORD PTR [ecx+041a6a8h] U 0x115c 0.06% mov bl, dl 1 V 0x115e 0.05% mov cl, dh U * 0x1160 0.16% xor esi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x1166 0.10% shr edx, 16 1 PU_Inst V 0x1169 0.13% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x116f 0.09% mov bl, dl 1 V 0x1171 0.06% mov cl, dh U * 0x1173 0.19% xor esi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x1179 0.13% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x117f 0.11% xor esi, eax 1 V 0x1181 0.06% mov edx, DWORD PTR [ebp+20] U 0x1184 0.06% mov eax, DWORD PTR [ebp+16] 1 V 0x1187 0.05% xor edx, esi U 0x1189 0.05% xor eax, esi 1 W 0x118b 0.07% ror edx, 4 1 PU_Inst V 0x118e 0.13% and eax, -03030304h U 0x1193 0.04% and edx, -03030304h 1 V 0x1199 0.07% mov bl, al U 0x119b 0.06% mov cl, ah 1 V * 0x119d 0.16% xor edi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x11a3 0.11% shr eax, 16 1 V * 0x11a6 0.11% xor edi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x11ac 0.11% mov bl, al 1 V 0x11ae 0.04% mov cl, ah U * 0x11b0 0.18% xor edi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x11b6 0.10% mov eax, DWORD PTR [ecx+041a6a8h] U 0x11bc 0.08% mov bl, dl 1 V 0x11be 0.05% mov cl, dh U * 0x11c0 0.17% xor edi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x11c6 0.11% shr edx, 16 1 PU_Inst V 0x11c9 0.13% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x11cf 0.09% mov bl, dl 1 V 0x11d1 0.06% mov cl, dh U * 0x11d3 0.17% xor edi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x11d9 0.13% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x11df 0.08% xor edi, eax 1 V 0x11e1 0.06% mov edx, DWORD PTR [ebp+28] U 0x11e4 0.06% mov eax, DWORD PTR [ebp+24] 1 V 0x11e7 0.04% xor edx, edi U 0x11e9 0.06% xor eax, edi 1 W 0x11eb 0.05% ror edx, 4 1 PU_Inst V 0x11ee 0.11% and eax, -03030304h U 0x11f3 0.04% and edx, -03030304h 1 V 0x11f9 0.06% mov bl, al U 0x11fb 0.06% mov cl, ah 1 V * 0x11fd 0.16% xor esi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x1203 0.12% shr eax, 16 1 V * 0x1206 0.13% xor esi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x120c 0.12% mov bl, al 1 V 0x120e 0.05% mov cl, ah U * 0x1210 0.19% xor esi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x1216 0.12% mov eax, DWORD PTR [ecx+041a6a8h] U 0x121c 0.07% mov bl, dl 1 V 0x121e 0.05% mov cl, dh U * 0x1220 0.18% xor esi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x1226 0.09% shr edx, 16 1 PU_Inst V 0x1229 0.12% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x122f 0.11% mov bl, dl 1 V 0x1231 0.06% mov cl, dh U * 0x1233 0.17% xor esi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x1239 0.11% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x123f 0.11% xor esi, eax 1 V 0x1241 0.05% mov edx, DWORD PTR [ebp+36] U 0x1244 0.06% mov eax, DWORD PTR [ebp+32] 1 V 0x1247 0.06% xor edx, esi U 0x1249 0.05% xor eax, esi 1 W 0x124b 0.06% ror edx, 4 1 PU_Inst V 0x124e 0.13% and eax, -03030304h U 0x1253 0.05% and edx, -03030304h 1 V 0x1259 0.06% mov bl, al U 0x125b 0.08% mov cl, ah 1 V * 0x125d 0.17% xor edi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x1263 0.13% shr eax, 16 1 V * 0x1266 0.10% xor edi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x126c 0.13% mov bl, al 1 V 0x126e 0.05% mov cl, ah U * 0x1270 0.19% xor edi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x1276 0.11% mov eax, DWORD PTR [ecx+041a6a8h] U 0x127c 0.08% mov bl, dl 1 V 0x127e 0.05% mov cl, dh U * 0x1280 0.21% xor edi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x1286 0.12% shr edx, 16 1 PU_Inst V 0x1289 0.14% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x128f 0.09% mov bl, dl 1 V 0x1291 0.06% mov cl, dh U * 0x1293 0.16% xor edi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x1299 0.15% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x129f 0.10% xor edi, eax 1 V 0x12a1 0.07% mov edx, DWORD PTR [ebp+44] U 0x12a4 0.08% mov eax, DWORD PTR [ebp+40] 1 V 0x12a7 0.05% xor edx, edi U 0x12a9 0.04% xor eax, edi 1 W 0x12ab 0.06% ror edx, 4 1 PU_Inst V 0x12ae 0.14% and eax, -03030304h U 0x12b3 0.05% and edx, -03030304h 1 V 0x12b9 0.06% mov bl, al U 0x12bb 0.07% mov cl, ah 1 V * 0x12bd 0.15% xor esi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x12c3 0.12% shr eax, 16 1 V * 0x12c6 0.12% xor esi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x12cc 0.11% mov bl, al 1 V 0x12ce 0.04% mov cl, ah U * 0x12d0 0.17% xor esi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x12d6 0.10% mov eax, DWORD PTR [ecx+041a6a8h] U 0x12dc 0.08% mov bl, dl 1 V 0x12de 0.05% mov cl, dh U * 0x12e0 0.18% xor esi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x12e6 0.10% shr edx, 16 1 PU_Inst V 0x12e9 0.13% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x12ef 0.12% mov bl, dl 1 V 0x12f1 0.05% mov cl, dh U * 0x12f3 0.16% xor esi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x12f9 0.13% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x12ff 0.11% xor esi, eax 1 V 0x1301 0.07% mov edx, DWORD PTR [ebp+52] U 0x1304 0.08% mov eax, DWORD PTR [ebp+48] 1 V 0x1307 0.04% xor edx, esi U 0x1309 0.05% xor eax, esi 1 W 0x130b 0.07% ror edx, 4 1 PU_Inst V 0x130e 0.14% and eax, -03030304h U 0x1313 0.04% and edx, -03030304h 1 V 0x1319 0.06% mov bl, al U 0x131b 0.09% mov cl, ah 1 V * 0x131d 0.16% xor edi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x1323 0.13% shr eax, 16 1 V * 0x1326 0.11% xor edi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x132c 0.12% mov bl, al 1 V 0x132e 0.05% mov cl, ah U * 0x1330 0.19% xor edi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x1336 0.11% mov eax, DWORD PTR [ecx+041a6a8h] U 0x133c 0.07% mov bl, dl 1 V 0x133e 0.05% mov cl, dh U * 0x1340 0.18% xor edi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x1346 0.11% shr edx, 16 1 PU_Inst V 0x1349 0.14% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x134f 0.08% mov bl, dl 1 V 0x1351 0.06% mov cl, dh U * 0x1353 0.16% xor edi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x1359 0.13% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x135f 0.12% xor edi, eax 1 V 0x1361 0.05% mov edx, DWORD PTR [ebp+60] U 0x1364 0.07% mov eax, DWORD PTR [ebp+56] 1 V 0x1367 0.05% xor edx, edi U 0x1369 0.04% xor eax, edi 1 W 0x136b 0.06% ror edx, 4 1 PU_Inst V 0x136e 0.13% and eax, -03030304h U 0x1373 0.04% and edx, -03030304h 1 V 0x1379 0.06% mov bl, al U 0x137b 0.06% mov cl, ah 1 V * 0x137d 0.17% xor esi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x1383 0.12% shr eax, 16 1 V * 0x1386 0.11% xor esi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x138c 0.11% mov bl, al 1 V 0x138e 0.04% mov cl, ah U * 0x1390 0.17% xor esi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x1396 0.11% mov eax, DWORD PTR [ecx+041a6a8h] U 0x139c 0.07% mov bl, dl 1 V 0x139e 0.05% mov cl, dh U * 0x13a0 0.16% xor esi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x13a6 0.09% shr edx, 16 1 PU_Inst V 0x13a9 0.13% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x13af 0.10% mov bl, dl 1 V 0x13b1 0.06% mov cl, dh U * 0x13b3 0.18% xor esi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x13b9 0.14% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x13bf 0.09% xor esi, eax 1 V 0x13c1 0.05% mov edx, DWORD PTR [ebp+68] U 0x13c4 0.06% mov eax, DWORD PTR [ebp+64] 1 V 0x13c7 0.05% xor edx, esi U 0x13c9 0.06% xor eax, esi 1 W 0x13cb 0.07% ror edx, 4 1 PU_Inst V 0x13ce 0.11% and eax, -03030304h U 0x13d3 0.05% and edx, -03030304h 1 V 0x13d9 0.05% mov bl, al U 0x13db 0.07% mov cl, ah 1 V * 0x13dd 0.15% xor edi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x13e3 0.13% shr eax, 16 1 V * 0x13e6 0.11% xor edi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x13ec 0.11% mov bl, al 1 V 0x13ee 0.05% mov cl, ah U * 0x13f0 0.18% xor edi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x13f6 0.11% mov eax, DWORD PTR [ecx+041a6a8h] U 0x13fc 0.07% mov bl, dl 1 V 0x13fe 0.05% mov cl, dh U * 0x1400 0.18% xor edi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x1406 0.10% shr edx, 16 1 PU_Inst V 0x1409 0.13% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x140f 0.09% mov bl, dl 1 V 0x1411 0.06% mov cl, dh U * 0x1413 0.17% xor edi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x1419 0.14% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x141f 0.11% xor edi, eax 1 V 0x1421 0.06% mov edx, DWORD PTR [ebp+76] U 0x1424 0.08% mov eax, DWORD PTR [ebp+72] 1 V 0x1427 0.04% xor edx, edi U 0x1429 0.05% xor eax, edi 1 W 0x142b 0.04% ror edx, 4 1 PU_Inst V 0x142e 0.12% and eax, -03030304h U 0x1433 0.06% and edx, -03030304h 1 V 0x1439 0.06% mov bl, al U 0x143b 0.07% mov cl, ah 1 V * 0x143d 0.15% xor esi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x1443 0.13% shr eax, 16 1 V * 0x1446 0.12% xor esi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x144c 0.11% mov bl, al 1 V 0x144e 0.05% mov cl, ah U * 0x1450 0.18% xor esi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x1456 0.11% mov eax, DWORD PTR [ecx+041a6a8h] U 0x145c 0.07% mov bl, dl 1 V 0x145e 0.04% mov cl, dh U * 0x1460 0.18% xor esi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x1466 0.09% shr edx, 16 1 PU_Inst V 0x1469 0.11% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x146f 0.11% mov bl, dl 1 V 0x1471 0.06% mov cl, dh U * 0x1473 0.17% xor esi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x1479 0.15% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x147f 0.11% xor esi, eax 1 V 0x1481 0.06% mov edx, DWORD PTR [ebp+84] U 0x1484 0.06% mov eax, DWORD PTR [ebp+80] 1 V 0x1487 0.04% xor edx, esi U 0x1489 0.05% xor eax, esi 1 W 0x148b 0.07% ror edx, 4 1 PU_Inst V 0x148e 0.10% and eax, -03030304h U 0x1493 0.05% and edx, -03030304h 1 V 0x1499 0.06% mov bl, al U 0x149b 0.09% mov cl, ah 1 V * 0x149d 0.14% xor edi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x14a3 0.14% shr eax, 16 1 V * 0x14a6 0.10% xor edi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x14ac 0.12% mov bl, al 1 V 0x14ae 0.06% mov cl, ah U * 0x14b0 0.17% xor edi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x14b6 0.10% mov eax, DWORD PTR [ecx+041a6a8h] U 0x14bc 0.08% mov bl, dl 1 V 0x14be 0.07% mov cl, dh U * 0x14c0 0.17% xor edi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x14c6 0.10% shr edx, 16 1 PU_Inst V 0x14c9 0.14% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x14cf 0.10% mov bl, dl 1 V 0x14d1 0.06% mov cl, dh U * 0x14d3 0.16% xor edi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x14d9 0.12% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x14df 0.09% xor edi, eax 1 V 0x14e1 0.06% mov edx, DWORD PTR [ebp+92] U 0x14e4 0.07% mov eax, DWORD PTR [ebp+88] 1 V 0x14e7 0.06% xor edx, edi U 0x14e9 0.04% xor eax, edi 1 W 0x14eb 0.06% ror edx, 4 1 PU_Inst V 0x14ee 0.12% and eax, -03030304h U 0x14f3 0.05% and edx, -03030304h 1 V 0x14f9 0.06% mov bl, al U 0x14fb 0.07% mov cl, ah 1 V * 0x14fd 0.14% xor esi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x1503 0.11% shr eax, 16 1 V * 0x1506 0.12% xor esi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x150c 0.12% mov bl, al 1 V 0x150e 0.05% mov cl, ah U * 0x1510 0.19% xor esi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x1516 0.11% mov eax, DWORD PTR [ecx+041a6a8h] U 0x151c 0.07% mov bl, dl 1 V 0x151e 0.05% mov cl, dh U * 0x1520 0.17% xor esi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x1526 0.10% shr edx, 16 1 PU_Inst V 0x1529 0.13% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x152f 0.10% mov bl, dl 1 V 0x1531 0.05% mov cl, dh U * 0x1533 0.15% xor esi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x1539 0.14% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x153f 0.10% xor esi, eax 1 V 0x1541 0.07% mov edx, DWORD PTR [ebp+100] U 0x1544 0.07% mov eax, DWORD PTR [ebp+96] 1 V 0x1547 0.04% xor edx, esi U 0x1549 0.04% xor eax, esi 1 W 0x154b 0.06% ror edx, 4 1 PU_Inst V 0x154e 0.11% and eax, -03030304h U 0x1553 0.04% and edx, -03030304h 1 V 0x1559 0.06% mov bl, al U 0x155b 0.08% mov cl, ah 1 V * 0x155d 0.15% xor edi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x1563 0.12% shr eax, 16 1 V * 0x1566 0.12% xor edi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x156c 0.14% mov bl, al 1 V 0x156e 0.04% mov cl, ah U * 0x1570 0.18% xor edi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x1576 0.11% mov eax, DWORD PTR [ecx+041a6a8h] U 0x157c 0.09% mov bl, dl 1 V 0x157e 0.06% mov cl, dh U * 0x1580 0.17% xor edi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x1586 0.10% shr edx, 16 1 PU_Inst V 0x1589 0.14% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x158f 0.10% mov bl, dl 1 V 0x1591 0.05% mov cl, dh U * 0x1593 0.17% xor edi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x1599 0.13% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x159f 0.10% xor edi, eax 1 V 0x15a1 0.05% mov edx, DWORD PTR [ebp+108] U 0x15a4 0.06% mov eax, DWORD PTR [ebp+104] 1 V 0x15a7 0.05% xor edx, edi U 0x15a9 0.05% xor eax, edi 1 W 0x15ab 0.06% ror edx, 4 1 PU_Inst V 0x15ae 0.13% and eax, -03030304h U 0x15b3 0.05% and edx, -03030304h 1 V 0x15b9 0.05% mov bl, al U 0x15bb 0.06% mov cl, ah 1 V * 0x15bd 0.14% xor esi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x15c3 0.12% shr eax, 16 1 V * 0x15c6 0.11% xor esi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x15cc 0.11% mov bl, al 1 V 0x15ce 0.06% mov cl, ah U * 0x15d0 0.18% xor esi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x15d6 0.10% mov eax, DWORD PTR [ecx+041a6a8h] U 0x15dc 0.08% mov bl, dl 1 V 0x15de 0.05% mov cl, dh U * 0x15e0 0.19% xor esi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x15e6 0.09% shr edx, 16 1 PU_Inst V 0x15e9 0.14% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x15ef 0.09% mov bl, dl 1 V 0x15f1 0.06% mov cl, dh U * 0x15f3 0.19% xor esi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x15f9 0.14% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x15ff 0.12% xor esi, eax 1 V 0x1601 0.07% mov edx, DWORD PTR [ebp+116] U 0x1604 0.07% mov eax, DWORD PTR [ebp+112] 1 V 0x1607 0.04% xor edx, esi U 0x1609 0.04% xor eax, esi 1 W 0x160b 0.06% ror edx, 4 1 PU_Inst V 0x160e 0.14% and eax, -03030304h U 0x1613 0.04% and edx, -03030304h 1 V 0x1619 0.06% mov bl, al U 0x161b 0.07% mov cl, ah 1 V * 0x161d 0.15% xor edi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x1623 0.14% shr eax, 16 1 V * 0x1626 0.12% xor edi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x162c 0.13% mov bl, al 1 V 0x162e 0.06% mov cl, ah U * 0x1630 0.17% xor edi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x1636 0.11% mov eax, DWORD PTR [ecx+041a6a8h] U 0x163c 0.07% mov bl, dl 1 V 0x163e 0.05% mov cl, dh U * 0x1640 0.18% xor edi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x1646 0.09% shr edx, 16 1 PU_Inst V 0x1649 0.13% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x164f 0.09% mov bl, dl 1 V 0x1651 0.06% mov cl, dh U * 0x1653 0.17% xor edi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x1659 0.11% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x165f 0.10% xor edi, eax 1 V 0x1661 0.06% mov edx, DWORD PTR [ebp+124] U 0x1664 0.06% mov eax, DWORD PTR [ebp+120] 1 V 0x1667 0.05% xor edx, edi U 0x1669 0.04% xor eax, edi 1 W 0x166b 0.06% ror edx, 4 1 PU_Inst V 0x166e 0.13% and eax, -03030304h U 0x1673 0.04% and edx, -03030304h 1 V 0x1679 0.06% mov bl, al U 0x167b 0.07% mov cl, ah 1 V * 0x167d 0.17% xor esi, DWORD PTR [ebx[des_SPtrans (10a8h)]] 3-1 Exp_AGI_V_Pen:1 U 0x1683 0.11% shr eax, 16 1 V * 0x1686 0.11% xor esi, DWORD PTR [ecx+041a2a8h] 3-1 Exp_AGI_U_Pen:1 U 0x168c 0.11% mov bl, al 1 V 0x168e 0.05% mov cl, ah U * 0x1690 0.18% xor esi, DWORD PTR [ebx+041a4a8h] 3 Exp_AGI_U_Pen:1 V 0x1696 0.13% mov eax, DWORD PTR [ecx+041a6a8h] U 0x169c 0.07% mov bl, dl 1 V 0x169e 0.05% mov cl, dh U * 0x16a0 0.16% xor esi, DWORD PTR [ebx+041a1a8h] 3 Exp_AGI_U_Pen:1 W 0x16a6 0.10% shr edx, 16 1 PU_Inst V 0x16a9 0.12% xor eax, DWORD PTR [ecx+041a3a8h] 2-1 U 0x16af 0.09% mov bl, dl 1 V 0x16b1 0.07% mov cl, dh U * 0x16b3 0.18% xor esi, DWORD PTR [ebx+041a5a8h] 3 Exp_AGI_U_Pen:1 V 0x16b9 0.12% xor eax, DWORD PTR [ecx+041a7a8h] 2-1 U 0x16bf 0.09% xor esi, eax 1 V 0x16c1 0.06% jmp des_encrypt+c8a (1cc6h)

1 0

Re: encryption program
by Liz Taylor 17 Dec '03

17 Dec '03

Ed Falk wrote: > > I ran a quick Kappa test on it. There was a nice fat spike at key > length 25, as somebody else suggested, but an almost perfect > correlation at 100. The message is almost certainly a simple > polyalphabetic cipher with keylength 100. I don't want to discourage anybody from trying their cryptanalytic skills against this, but this particular cryptogram has already been decrypted and the plain text posted to sci.crypt a few days back by Jim Gillogly. The message ID is <32D445A4.3DF(a)mentat.com> The snake oil vendor then came out with another cryptogram using the same algorithm. It is titled `decryption' and the plain text starts with "There are plenty of programs you could buy such as". Mr. Gillogly broke that too. See news:<32DA7FE4.1F41(a)mentat.com> -- Diamonds are a girl's best friend.

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Re: RSA challenge: is it legal to try?
by nobody＠replay.com 17 Dec '03

17 Dec '03

Greg Broiles says, Ian Goldberg wrote: > > >According to http://www.rsa.com/rsalabs/newfaq/q76.html, RSA is in the > >process of patent application for RC5. Does that mean it's illegal to > >write a keysearch program for the RC5 challenges (unless you use BSAFE > >or something like that)? Patents only apply to commercial use. I don't think participating in the contest can be considered commerical use. Me, a lawyer? No way.

1 0

a cool place to crash
by spiderman＠emirates.net.ae 17 Dec '03

17 Dec '03

If any of u guys wanna crash a site on the net try this one : www.emirates.net.ae enjoy ....................................

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RE: encryption program
by Mullen Patrick 17 Dec '03

17 Dec '03

What is a Kappa test? Is there software I can run to perform such a test? Where can I get it? Thanks! Patrick _______________________________________________________________________________ From: Ed Falk on Mon, Jan 13, 1997 20:33 I ran a quick Kappa test on it. There was a nice fat spike at key length 25, as somebody else suggested, but an almost perfect correlation at 100. The message is almost certainly a simple polyalphabetic cipher with keylength 100. I've been playing with it, and have maybe 5% of it decoded. It's full of really blatent clues. Kind of fun.

1 0