I 'spose it's gettin' to be time that we ditched them 512 bit keys and them 40 bit keys. :) The very existance of a 2.6GHz CPU - yes freon cooled is more than enough... =====================================Kaos=Keraunos=Kybernetos============== .+.^.+.| Ray Arachelian |Prying open my 3rd eye. So good to see |./|\. ..\|/..|sunder@sundernet.com|you once again. I thought you were |/\|/\ <--*-->| ------------------ |hiding, and you thought that I had run |\/|\/ ../|\..| "A toast to Odin, |away chasing the tail of dogma. I opened|.\|/. .+.v.+.|God of screwdrivers"|my eye and there we were.... |..... ======================= http://www.sundernet.com ========================== ---------- Forwarded message ---------- Date: Wed, 17 Sep 1997 11:08:40 -0500 From: "Kirk R. Erichsen" <KirkE@LOSNINOS.ORG> Reply-To: AlphaNT@beauty.mke.ra.rockwell.com To: AlphaNT@beauty.mke.ra.rockwell.com Subject: Re: 767 MHz Alpha, opinion_mode_enabled According to trade reports, the 21264 will be available at 800MHz by mid 98 but the die size (a .25 micron die) will need a signficant shrink to make the speed practical (heat and power consumption will be monsterous). It will need a die shrink to a .15 or .18 process in order for 800MHz + Alpha CPUs to be inexpensive enough to produce in volume. A smaller die size increases the number of chips that are "good" per waffer and decreases the finished chips power consumption and heat dissipation. Other methods for dealing with CPU speed (which don't address power or heat directly) include using CMOS alternatives like BiCMOS and Gallium Arsenide. Gallium Arsenide is very expensive, and the element Gallium is a rare earth element, so high production using it is not possible. As for the existing Digital freon "lab" chips, the 1.2GHz frequency has actually been surpassed twice already, with some reports saying that the last test with a non-production (beta 21364?) chip reached 2.6GHz. I don't know if at that frequency the processor was at sub-zero (in Celsius) temperatures, but it was at least a liquid nitrogen machine. One question no one seems to ask is "how fast were the external buses to memory and cache running on these testbeds?" Xray lithography has already produced (in very limited quantity) operable memory and processors with die sizes of below .000001 microns, a size that could accomodate about 1000 21264 processors in a package that would appear to be little more than a single "chip." The problem with implementing Xray lithography is that almost none of the existing process tools for producing chips can be used. The precise photo lithography masks (most of which are used with ultra-violet light) don't work anymore (Xray just goes right through) forcing you to use alloys of lead, bismuth and zirconium in the masks, a considerably more expensive and complex method. Ionizer units and other tools would have to be built for dealing with incredibly low tolerance. When Xray lithography is finally implmented, there will be a quantum lead in the frequency (multi GHz) while simulataneously reducing power consumption and heat dissipation. SMP and massively parallel machines will be portable boxes that will weigh only slightly more than the case and screen (if the TFT panel itself does not fall prey to light weight projection glasses) force it to be. The other option for new memory and processor devices is to "grow" them. Nanotechnologies that may be available in the next 10 years could allow microscopic machines in combination with biologic engineering could produce processors and memory of sizes at or below those of Xray lithography, with significant implications in other industries as well. One issue very rarely addressed in trade mags is the system bus speeds for the system bus (or any seperate cache, memory and I/O buses). Without a fast external bus speed, the system cannot necessarily provide more usable performance, particularly when memory becomes bottlenecked and saturated even at todays low frequencies. High internal CPU frequency does can not provide a linear increase in performance in and of itself. At about 400MHz, you have reached the maximum frequency an electrical bus can run. The next option for connecting the system bus to the processors is through optical buses. Optical buses don't suffer from the interference and noise that electrical buses do, and can operate at up to many thousands of GB without the error rates. Optical buses will connect all cache, memory and storage devices (directly without I/O adaption) in multiple segments with parallel access to all devices. The problems with doing this are the speed of the embedded switches which convert electrical signals into optical pulses are currently much too high in latency. A die shrink, the use of a high speed silicon or GA switch (or some new Selenium technology) could make the speed between electrical and optical buses practical. The other implication of more advanced methods for producing memory and processors is that the sluggish mechanical disk drive becomes totally obsolete. Massive non-volatile memory storage could be added to a system directly off the memory bus without the need for additional I/O buses. Hologramic optical storage devices (which store data as an image in 3D space) will replace most of the mechanical drive based multi-terrabyte installations with multi exabyte storage that will be 1000 smaller than existing storage devices. The entire world could place all its currently existing data and archives into a hologramic memory device the size of a lunch box. If it all sounds far fetched, its been proven possible already. Lets give it 10 years. At 10:41 AM 9/17/97 -0400, you wrote:

I talked with a tech from DEC here in Massachusetts and yes, I can confirm that they did get 1.2 Gig but it was cooled with a liquid nitrogen containing fan system, which cooled the chip considerably, but not below freezing point. The FPU was very bad at this temp though

Kirk R. Erichsen LAN Manager/Communications