At 02:14 AM 7/31/96 -0800, Jim McCoy wrote:

The interconnection problem has also been solved in this chip series. [A long-standing problem with FPGAs is that there were generally a limited amount of "wires" running between the logic elements and thus a lot of cells were wasted because there were no interconnections left, I/O to the outside world was also a problem.] The chip has a really cool interconnection method which allows a much more efficient use of the chip real estate and which makes the entire chip directly addresable (like regular RAM) through an on-chip interface module. Given the relatively compact design in Ian and Dave's paper and the new chips one might even fit two or four cracking engines on a single FPGA.

However, I think it very unlikely that an organization like the NSA would bother with an FPGA to do a cracking engine. FPGA's have substantial limitations, as you alluded to above, due to the need to make them "general purpose." A non-field programmable Gate Array, a hard-wired chip, would tend to optimize the interconnections on chip including minimizing the delays, but not incur the full-custom costs such as the penalty for low volume. Jim Bell jimbell@pacifier.com