SHA1 broken?

[Tyler Durden]

Ah. You meant as a principal in general. Of course the prevailing wisdom is 
to go from FPGAs to ASICs when you have heavy tasks.

In Telecom equipment, however, there's a few issues that basically 'require' 
FPGAs.

First, the standards change quite a bit, depending on which area you're in. 
For instance, RPR didn't really get settled until very recently. Second, 
your customers may ask for "more" or different kinds of functionality, so 
you may have a new release of firmware to address that. Putting the framing 
and/or PM on an FPGA while keeping the guts (eg, packet processing) on the 
main ASIC/processor allows you to swap out the trivial without a major heart 
transplant.

In addition, there's probably the far more important issue of design cycle 
times. ASICs will take (at the very minimum) 18 months to create, and if you 
make a mistake early on and don't catch, you have to start all over again. 
For some fields that's just unacceptable.

Then again, if you're looking for sheer, brute performance and design cycle 
times are not a limiting factor, ASICs are often the way to go. Even in a 
Variola Suitcase, however, I'd bet some of the trivial functions are 
off-loaded to an FPGA, though, for reasons above.

-TD

>From: "Riad S. Wahby" <rsw at jfet.org>
>To: cypherpunks at al-qaeda.net
>Subject: Re: SHA1 broken?
>Date: Tue, 8 Mar 2005 13:26:48 -0600
>
>Tyler Durden <camera_lumina at hotmail.com> wrote:
> > Well, maybe I misunderstand your statement here, but in Telecom most 
>heavy
> > iron has plenty of FPGAs, and as far as I understand it, they more or 
>less
> > have to.
>
>Have to in what sense?  If they're constantly reconfiguring the FPGAs
>(new software revs, or some sort of evolutionary "learning" process---
>the latter not likely in telecom, of course), sure, they have  to be on
>reprogrammable structures.
>
>If, on the other hand, you're building a custom hash cracking machine,
>you don't need to reconfigure your gates. You could design your
>parallelized SHA1 cracking machine and dump it onto a bunch of FPGAs,
>but if you really have unlimited resources you take the plunge into
>ASICs, at which point you can tighten your timing substantially.
>
>--
>Riad S. Wahby
>rsw at jfet.org