It seems it would be really good to log the pin behaviors at the chip.
   This is hard for me, due to inhibitions around logic probes.
   The concept is easier if I split it into two parts. The connection at
   the chip could be discerned canonically by using new sockets and chips.
   Then I could add a wire to every 2.54 mm pin to log it, without
   worrying about surface mount socket stuff.