X86 dispatch contention vulnerability

jim bell jdb10987 at yahoo.com
Sat Nov 17 13:48:29 PST 2018

 On Friday, November 16, 2018, 12:15:13 PM PST, juan <juan.g71 at gmail.com> wrote:
 On Thu, 15 Nov 2018 23:25:18 +0000 (UTC)
jim bell <jdb10987 at yahoo.com> wrote:

>> When I worked for Intel (1980-1982), a typical silicon linewidth was 3 microns.  (3000 nanometers.)  Recently I saw that Intel was using a 10 nanometer process, 300x smaller in linear size, and (300x)**2  (90,000) smaller in area.   What's truly amazing is how they have come to be able to etch such small feature-sizes on silicon.   For a long time, they were using 193 (?) nanometer UV light to do that, and yet they got feature-sizes below 50 nanometers. 

 >   Yes, that's interesting. At first I naively assumed that you couldn't print stuff smaller than the wavelength used but that's not the case at all.

That's actually a good first-approximation, at least prior to the insertion of a few billion dollars of research into better optical methods.  I recall an analogy, 'How do you draw a 1 millimeter line on paper, if you only have a 5-millimeter paintbrush?" 
  In the 1960's and much of the 1970's, they used something called "contact printing", basically pressing a chromium-on-quartz optical mask onto the wafer with the photoresist previously applied.  That worked, except that the masks didn't last very long.  Then they went to "projection printers", which separated the mask from the wafers.  Then, they went to "step and repeat" systems   https://en.wikipedia.org/wiki/Stepper   , which projected only the image of a single chip onto the wafer at a time, precisely repeated across the area of the wafer.
  "Steppers", as they were called, became important because it was hard to match the temperature coefficient  of expansion of a silicon wafer   http://www.ioffe.ru/SVA/NSM/Semicond/Si/thermal.html  2.6 ppm/degree C, to the temperature coefficient of a silica photomask  https://www.accuratus.com/fused.html   0.55 ppm/degree C.  Consider that if the feature-size they wish to draw is 100 nanometer, and the distance across the (silicon) wafer is 300 millimeters.  That's 1 part in 3 million!!!   They would have had to thermostat the temperatures of the silicon and silica to well better than 0.1 degrees C!! Using a wafer-stepper meant that they only had to do this alignment over a relatively small distance, maybe about 1 centimeter.  Far easier than 30 centimeters. 
I have seen articles about the various weird optical tricks used to allow the writing of much-less-than-wavelength features on chips.  I think one was in Scientific American about 10 years ago.   In these, the mask looks little like the eventual features you want to produce:  They "pre-calculate" the various optical distortions that they know the light will be subjected to, along with issues such as the sensitivity of the photoresist. 

However, these 'tricks' eventually run out of gas.  For a long time, they used 193 nanometer UV "light", https://en.wikipedia.org/wiki/Photolithography     That was somewhat of a limit, mostly because they could not find an easy way to generate UV at a shorter wavelength than 193.  

>>(using a lot of photolithographic 'tricks' to do so!.)  Now, I think they probably use "EUV", short for "Extreme Ultraviolet", which amounts to soft-xrays, maybe at about 10nm wavelength or even shorter.   https://en.wikipedia.org/wiki/Extreme_ultraviolet     

 >   Yeah, the accuracy is impressive. Now, from a libertarian point of view, there's a huge accumulation of knowledge and 'capital' in the hands of very few people. Also, many of these  developments are govt subsidized in many ways and end up in the hands of a few monopolistic businesses. What this boils down to of course is the fact that the infrastructure is fully controlled by the enemy. 

There is still a lot of chip-making which does not need  to be done at these "bleeding-edge" levels.  Microprocessors and memory chips, primarily, need to have the smallest features.  
               Jim Bell

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