X86 dispatch contention vulnerability

[jim bell]

    On Thursday, November 15, 2018, 12:49:56 PM PST, juan <juan.g71 at gmail.com> wrote:  
 
 On Wed, 14 Nov 2018 21:15:29 +0000 (UTC)
jim bell <jdb10987 at yahoo.com> wrote:


me >>    IIRC you also worked for intel designing memory chips? Excuse my rather naive question but...Did you see/hear at that time any hints that chips  were being tampered with or somehow backdooored  because of 'national security'? 

>> I didn't design memory chips.  I was a "product engineer" for a specific self-refreshing dynamic RAM 

 >   I guess I didn't recall correctly then =P . I must have assumed that product engineer more or less meant designer. 


A "design engineer" is a person who designs the circuitry.  A "process engineer" is a person who specializes in the chemistry, photolithography, ion implantation, etching, and other steps involved in the creation of a processed silicon wafer.  The whole process is amazingly complicated.
When I worked for Intel (1980-1982), a typical silicon linewidth was 3 microns.  (3000 nanometers.)  Recently I saw that Intel was using a 10 nanometer process, 300x smaller in linear size, and (300x)**2  (90,000) smaller in area.   What's truly amazing is how they have come to be able to etch such small feature-sizes on silicon.   For a long time, they were using 193 (?) nanometer UV light to do that, and yet they got feature-sizes below 50 nanometers. (using a lot of photolithographic 'tricks' to do so!.)  Now, I think they probably use "EUV", short for "Extreme Ultraviolet", which amounts to soft-xrays, maybe at about 10nm wavelength or even shorter.   https://en.wikipedia.org/wiki/Extreme_ultraviolet     

https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithography>> In fact, I was the first person at Intel, and perhaps in the world, who saw the flash(es) through the microscope of the as-being-blown fuses on these chips.  Intel was doing this redundancy before anyone else, I believe. 

 >   Interesting. I thought that sort of patching was something relatively new only done to the chips in sdcards and the like. I guess it's not new. ×

No, it's definitely not new!   Although, it was somewhat hush-hush at the time.  Apparently the big chip-buyers might not have liked to hear of these 'repair' techniques.  They probably had these pictures in their minds of perfect chips emerging efficiently from the production line.  But, they also wanted to buy cheaper chips, and it was hard to make a truly-defect-free chip when you're trying to put 65,536 transistors into the array of a DRAM.  The more-sophisticated users no doubt were told of this technique, and they probably gave extra care to testing incoming parts.  

Hard-disk manufacturers probably characterize their platters in a similar way, looking for weak areas that have trouble recording data.  

                Jim Bell



  
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