SHA1 broken?

Riad S. Wahby rsw at jfet.org
Wed Mar 9 11:12:10 PST 2005


Tyler Durden <camera_lumina at hotmail.com> wrote:
> Then again, if you're looking for sheer, brute performance and design cycle 
> times are not a limiting factor, ASICs are often the way to go. Even in a 
> Variola Suitcase, however, I'd bet some of the trivial functions are 
> off-loaded to an FPGA, though, for reasons above.

Oh, sure.  Buy yourself the flexibility of the FPGA, e.g., by putting an
FPGA on a huge DMA pipe.  But don't count on the FPGA to do the brunt of
the crunching once you've settled on an implementation.

Note also that you can probably buy yourself lots of performance without
increasing the design cycle time all that much by simply synthesizing
(via Synopsys or the like) the same Verilog with which you would have
programmed the FPGA.  Buy (or pirate if you can; it's not like you're
selling these things, so who cares about the IP issues?) a set of
standard logic cells in the smallest process you can afford so that even
the lion's share of the layout can be done in a completely automated
fashion, and you're basically all set.

-- 
Riad S. Wahby
rsw at jfet.org





More information about the cypherpunks-legacy mailing list