----- Forwarded message from ron minnich <rminnich@gmail.com> ----- Date: Mon, 09 Mar 2015 03:06:07 +0000 From: ron minnich <rminnich@gmail.com> To: coreboot <coreboot@coreboot.org> Subject: [coreboot] Fwd: lowRISC in Google Summer of Code 2015 Message-ID: <CAP6exY+27t8R7sU552nf7aZTR_0jaP5kcmq3wOCPBV3zLv2+8Q@mail.gmail.com> ---------- Forwarded message --------- From: lowRISC Announcements <list@ann.lowrisc.org> Date: Sun, Mar 8, 2015 at 1:52 PM Subject: lowRISC in Google Summer of Code 2015 To: <rminnich@gmail.com> We're pleased to announce that lowRISC is taking part in Google Summer of Code as a mentoring organisation. We're working with a number of our friends in the wider free and open source software and hardware communities to provide a range of project ideas in a number of different implementation languages covering every level of the hardware/software stack. GSoC provides a stipend of $5500 for selected students to work on open source over the summer. Student applications open on Monday 16th March. For more information, see the GSoC FAQ <https://www.google-melange.com/gsoc/document/show/gsoc_ program/google/gsoc2015/help_page>. The full lowRISC ideas list is available here <http://www.lowrisc.org/docs/gsoc-2015-ideas/>, and the titles are listed below. We're also very interested in student-proposed ideas. Massive thanks are due to everyone who has volunteered to mentor. * A fully open source FPGA compilation flow using Yosys * Accessing the OpenCores ecosystem (implementing a Wishbone to TileLink bridge) * jor1k port to RISC-V * Extend Tavor to support directed generation of assembly test cases * Constrained randomised testing with coverage tracking in Cocotb * TCP offload to minion cores using rump kernels * Schematic Viewer for Netlists (SVG/JavaScript) * Porting Icarus Verilog to JavaScript using Emscripten * Optimized ray tracer for Nyuzi parallel processor * Porting musl libc to RISC-V * LLVM pass for control-flow hijacking protection using lowRISC’s tagged memory * Porting L4/FIASCO.OC to RISC-V * Adding Chisel support to FuseSoC * Trace Debugging Infrastructure for lowRISC * OCaml native code port to RISC-V * JTAG hardware debugging support for Nyuzi Even if you're not a student, we'd appreciate your help in spreading the word to ensure we get the best possible applicants. As ever, we invite you to subscribe to the lowrisc-dev discussion list <http://listmaster.pepperfish.net/cgi-bin/mailman/listinfo/ lowrisc-dev-lists.lowrisc.org>, idle on #lowRISC on irc.oftc.net, and follow @lowRISC on Twitter. -- The lowRISC team ------ If you wish to unsubscribe, click http://subscribe.lowrisc.org/ unsubscribe?email=rminnich%40gmail.com&secret=e66ba8262f518ffbe2fb50edd82c61 f0ed8f5c6a -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot ----- End forwarded message -----