Why is AEX implemented in SGX if Intel implemented x86 securely?
The buried lede in NEMESIS and FORESHADOW: For the “case of a fault or external interrupt, the processor executes an Asynchronous Enclave Exit (AEX) procedure that saves the execution context securely in a preallocated state save area inside the enclave, and replaces the CPU registers with a synthetic state to avoid di- rect information leakage to the untrusted ISR.” Seems. Odd. I dunno. Did anyone read x86 documentation?
Regrettably, the US government’s disinformation efforts has led to the total crippling and blinding of it’s own capacity to form any response without anyone actually able to understand Boyd. Arguably if anyone were to publicize that the entire apparatus is a Human-Ouroboros-Centipede it would virtually end this current bout of stupidity.
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Ryan Carboni