22 Apr
2015
22 Apr
'15
8:30 a.m.
On 4/17/15, coderman <coderman@gmail.com> wrote:
... for a not designed to fail bus between SoCs,
an SPI based ... if you trust these, then direct PCIe 4lane
someone else brought up DRAM fill over JTAG, other JTAG based comms. also not unreasonable, even if overkill for this purpose alone.