Boise, Idaho–based memory manufacturer Micron Technology says it has reached volume production of a 232-layer NAND flash-memory chip. It’s the first such chip to pass the 200-layer mark, and it’s been a tight race. Competitors are currently providing 176-layer technology, and some have said they are on track to follow Micron’s skyward move or already have working chips in hand.

The new Micron tech as much as doubles the density of bits stored per unit area versus competing chips, packing in 14.6 gigabits per square millimeter. Its 1-terabit chips are bundled into 2-terabyte packages, each of which is barely more than a centimeter on a side and can store about two weeks worth of 4K video.

With 81 trillion gigabytes (81 zettabytes) of data generated in 2021 and International Data Corp.
(IDC) predicting 221 ZB in 2026, “storage has to innovate to keep up,” says Alvaro Toledo, Micron’s vice president of data-center storage.

The move to 223 layers is a combination and extension of many technologies Micron has already deployed. To get a handle on them, you need to know the basic structure and function of 3D NAND flash. The chip itself is made up of a bottom layer of CMOS logic and other circuitry that’s responsible for controlling reading and writing operations and getting data on and off the chip as quickly and efficiently as possible. Improvements to this layer, such as optimizing the path data travels and reducing the capacitance of the chip’s inputs and outputs, yielded a 50 percent improvement in the data transfer rate to 2.4 Gb/s.

Above the CMOS are layers upon layers of NAND flash cells. Unlike other devices, Flash-memory cells are built vertically. They start as a (relatively) deep, narrow hole etched through alternating layers of conductor and insulator. Then the holes are filled with material and processed to form the bit-storing part of the device. It’s the ability to reliably etch and fill the holes through all those layers that’s a key limit to the technology. Instead of etching through all 232 layers in one go, Micron’s process builds them in two parts and stacks one atop the other. Even so, “it’s an astounding engineering feat,” says Alvaro. “That was one of the biggest challenges we overcame.”

According to Toledo, there is a path toward even more layers in future NAND chips. “There are definitely challenges,” he says. But “we haven’t seen the end of that path.”

In addition to adding more and more layers, NAND flash makers have been increasing the density of stored bits by packing multiple bits into a single device. Each of the Micron chip’s memory cells is capable of storing three bits per cell. That is, the charge stored in each cell produces a distinct enough effect to discern eight different states. Though 3-bit-per-cell products (called TLC) are the majority, four-bit products (called QLC) are also available. One QLC chip presented by Western Digital researchers at the IEEE International Solid State Circuits Conference earlier this year achieved a 15 Gb/mm² areal density in a 162-layer chip. And Kioxia engineers reported 5-bit cells last month at the IEEE Symposium on VLSI Technology and Circuits. There has even been a 7-bit cell demonstrated, but it required dunking the chip in 77-kelvin liquid nitrogen