Why is AEX implemented in SGX if Intel implemented x86 securely?

The buried lede in NEMESIS and FORESHADOW: For the “case of a fault or external interrupt, the processor executes an Asynchronous Enclave Exit (AEX) procedure that saves the execution context securely in a preallocated state save area inside the enclave, and replaces the CPU registers with a synthetic state to avoid di- rect information leakage to the untrusted ISR.” Seems. Odd. I dunno. Did anyone read x86 documentation?