C3 Nehemia C5P with better hardware RNG and AES support
News in from San Jose microprocessor forum: latest VIA C3 C5P does 1 GHz at 7 W power dissipation, has now two hardware RNG engines (and two x86 opcodes to read them), and an Advanced Cryptography Engine which can do AES (Rijndael128? doesn't say) at 12.5 GBit/s rate. Next-generation (Esther, early 2004) will add SHA-1 support in hardware. -- Eugen* Leitl <a href="http://leitl.org">leitl</a> ______________________________________________________________ ICBM: 48.07078, 11.61144 http://www.leitl.org 8B29F6BE: 099D 78BA 2FD3 B014 B08A 7779 75B0 2443 8B29 F6BE [demime 0.97c removed an attachment of type application/pgp-signature]
On Wed, Oct 15, 2003 at 05:14:17PM +0200, Eugen Leitl wrote:
News in from San Jose microprocessor forum:
latest VIA C3 C5P does 1 GHz at 7 W power dissipation, has now two hardware RNG engines (and two x86 opcodes to read them), and an Advanced Cryptography Engine which can do AES (Rijndael128? doesn't say) at 12.5 GBit/s rate.
Look at the PadLock ACE programming guide [1]. Only seems to support Rijndael with a block size of 128 bits (= AES); it allows both key scheduling in hardware and in software, the latter allowing you to have your own custom key schedule. It also allows you to increase the number of rounds if you think Rijndael-128's security margins are too low. Props to the VIA engineers for both the customizability. The errate are funny as well. Looks like the current stepping has a bug in the key schedule for 192 and 256 bit keys. Cheers, Ralf [1] VIA PadLock ACE programming guide http://www.via.com.tw/en/images/Products/eden/pdf/PadLock_ACE_prog_guide.pdf -- Ralf-P. Weinmann <rpw@uni.de>
participants (2)
-
Eugen Leitl -
Ralf-P. Weinmann