Tyler, Riad, etc: FPGAs are used in telecom because the volumes do not support an ASIC run. Riad doesn't seem to appreciate this. He does understand that an ASIC is more efficient because its gates are used only for 1 computation, rather than most (FPGA) gates being used for reconfigurability ---useful if you can't afford an ASIC run (a million bucks a mask...) or if algorithms get tweaked (eg you release before the Spec comes out, or you are shooting for time-to-market). Clockwise an FPGA wastes time in extra wire routing although since an FPGA may be made in state of the art processes, and your ASIC may not, its a complex tradeoff. (Albeit some circuit topologies work very well on FPGAs) So for the Cypherpunk wanting hardware (vs cluster) acceleration, FPGAs are the way to go. For TLAs, you prototype in FPGAs of course, and then make some chips in your private fab. (Same for Broadcom, etc.) For someone making 10,000 routers, you use FPGAs. DESCrack was solving a problem for which the x86 is not very efficient at computing --all the sub-byte bit-diddling-- and hardware is very efficient (by design in DES, after all).
"Major Variola (ret)" <mv@cdc.gov> wrote:
Riad doesn't seem to appreciate this.
Of course I do. I'm saying that for our purposes (a dedicated hashcracker) we want an ASIC. Whether we can afford one or not is another question (obviously if we can't, we buy the best FPGA we can). ...or are we no longer assuming an adversary with unlimited resources? -- Riad S. Wahby rsw@jfet.org
At 11:11 AM 3/19/2005, Major Variola (ret) wrote:
---useful if you can't afford an ASIC run (a million bucks a mask...)
...
For someone making 10,000 routers, you use FPGAs.
DESCrack was solving a problem for which the x86 is not very efficient at computing --all the sub-byte bit-diddling-- and hardware is very efficient (by design in DES, after all).
EFF's DESCrack cost $200K in 1998 and used ASICs. (It's really only six years since we killed off single-DES!) There were 1500 DES-cracker ASIC chips in it. ASICs may cost a bit more today - Moore's Law helps, but it also means that chip designs can become larger and more complex, though code-cracker applications have a lot of uniformity in their design, and we've got six more years of experience building ASIC cell libraries that can be reused. I suspect a similar-sized machine would cost a similar amount but have a lot more DES functional units in it. FPGAs probably make more sense for routers, because you want the ability to change the firmware more often, and a router has a bunch of other parts as well, and realistically, cypher-cracking is not an economically viable activity for most people, so the cost-benefit tradeoffs are a bit twisted.
FPGAs probably make more sense for routers, because you want the ability to change the firmware more often, and a router has a bunch of other parts as well, and realistically, cypher-cracking is not an economically viable activity for most people, so the cost-benefit tradeoffs are a bit twisted.
The router world seems to use a good mixture. At a startup we were purchasing nice off-the-shelf MPLS ASICs, which did MPLS route setup and forwarding (and some enforcement) while the 'software'/control plane (eg, OSPF, RSVP-TE, etc...) was largely in FPGAs of our own brew. At that time (ca, 2000/2001) some vendors were starting to push net processors, which were somewhere in between, and at the time just weren't quite fast enough for ASIC-busting applications and not quite flexible enough for FPGA-ish applications. Now, however, I'd bet net processors are very effective for metro-edge applications. What I suspect is that there's already some crypto net processors out there, though they may be classified, or the commercial equivalent (ie, I assume there are 'classified' catalogs from companies like General Dynamics that normal clients never see). They can periodically upgrade the code when they discover that some new form of stego (for instance) has become in-vogue at Al Qaeda. These won't be Variola Suitcase-type applications, though, but perhaps for special situations where they know the few locations in Cobble Hill Brooklyn they want to monitor and decrypt. -TD
participants (4)
-
Bill Stewart -
Major Variola (ret) -
Riad S. Wahby -
Tyler Durden