Re: Memory Management (fwd)

17 Dec 2003

      Forwarded message:
...
Date: Mon, 02 Feb 1998 23:01:16 -0600
From: Stu Green 
Subject: Re: Memory Management
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...
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I would imagine that the OS would keep a disk map in memory and
mark it with a flag to indicate if it's been paged into memory.
This is a function of the "Look Aside Buffer" and the actual operation is a
 bit more complicated.
...
Jim - I'm familiar with the 'translation look aside'buffers
on
RISC chips, especially on the MIPS where it provides a
method
of managing cache flushes and reloads on writes and does act
like a page fault to intiate the writes.  I haved seen TLBs
associated with disk operations, but that don't mean shit to
a
tree.
It turns out, I've been doing more reading on vmm on NT, that the model
that's implimented in NT is a hybrid of the MIPS 4000 model and the 386
model. That rationale is that this allows the actual code in the HAL to be
much smaller by taking advantage of the different hardware aspects of the
cpu architetures (this means speed).

Don't know if I am going to get this right since I still haven't figured out
all the intricacies. But this is what I *think* is going on (in NT)...

The TLB (Translation Lookaside Buffer) is used in NT to determine if the
page frame is currently in memory or swapped out. It does this by marking a
frame 'invalid' if it's swapped out and listing it's actual page frame
number if it's a valid page. Invalid does *not* mean that it can't still be
in memory. The reason is that each process has a 'Page Frame Directory' which
lists all the valid Page Table Pages for that process. Each of these Page
Table Pages lists where each Page Frame Page is within that processes memory
map (and that's a whole nother issue with various parts being pageable and
non-pageable as well as system or user level). Each Page Frame Page knowns
where the individual pages are (ie in memory or swapped out). There is a
rather tedious mechanism that translates the virtual addresses to PFD's,
PTP's, and finaly to PFP's. That's what I'm trying to get a handle on now.
Now these various page related structures get quite big and themselves need
to be swapped out. So there is a level of recursion in here. There is also a
Page Table Page structure called a 'Prototype PTE Address' (a PTE is a Page
Table Entry - ie a valid page frame, these things seem to have several
different names making it confusing to follow at times) which is used to
allow processes to share a PTE across PFD's. Once we get to a PTE we actualy
have a 4k chunk of code or data that a cpu can operate on/with.

So, there is where I'm at right now...

Hope that makes it clear as mud.

Naslajdyatciya!

ps. I am enjoying my Toshiba 445CDX, it's a pretty cool machine. Anyone
    got any suggestions on a PCMCIA ethernet card?

pss. Next Saturday is the 1st Saturday in Feb. so the Dallas 1st.
     Saturday Sale will be going on. Anyone interested? It's basicaly
     about 20 sq. blocks of computer equipment of every make, model,
     and age imaginable as well as lots of other stuff (time before
     last some guy had Cobra Helicopter IR cameras for $500 ea., would
     make a great IR telescope.). We usualy leave Saturday morning around
     2am and get there a bit before 7am. The sale usualy starts about
     midnite Friday nite and goes until Saturday evening. The best deals
     are early Saturday morning (my experience over about 5 years of
     going anyway).

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