On FPGAs:
And it is rather unlikely that one could make a high clock speed high performance hardware based key cracker work without traditional high speed logic debugging tools such as a fast logic analyzer (if we are talking 5-10 ns clock especially) and a 1 ghz or so digital scope. These kinds of gear, though sometimes available after hours to engineers working for more liberal companies or schools, cost many thousands of dollars and are not garden variety items available to any hacker.
Probably not necessary. Simulators do just fine. And the FPGAs themselves top out at 50 to 80 MHz.
And finally, depending on the technology of the part being used, there may be a significant cost in the order of at least hundreds if not thousands of dollars for a specialized programmer capable of programming ("burning") the FPGA with the interconnect patterns generated by the software. These tend to either be specialized to one kind of part and maybe modestly cheap (hundreds of dollars) or universal and several thousands of dollars (such as DataIO gear).
Easy to access. They are everywhere. The EPROMs are about $6 each and are serial. You could build a programmer at home.
And at least in my experiance (I may be unusually stupid and careless and clumsy or may not be) even if the parts are a few times reprogrammable (as CMOS FPGAs often are these days) one can assume that one will fry, or break the pins off, or reprogram one time too many the FPGA or FPGA's before one gets the design working. This means that it would be realistic to assume several parts would be consumed by the prototyping effort, they may not be cheap and this adds up too.
While there are OTP FPGAs out there (typocally Altera), many are in-circuit programmable *any* number of times since they use SRAM internally not EPROM cells to program the configuration. The latest twist on FPGAs is to add more RAM internally and have them reprogram themselves on the fly, hundreds of thousands of times a second. This cuts the logic requirements down for desidhns that don't need all of the logic all of the time.
So whilst someone working with these parts as part of their job or schooling might well have access to all the required resources on an informal basis and be able to build a key cracker in evenings or weekends for little more than the cost of the chip and a PC board to hold it, it should be realistically noted that the actual cost of equiping a lab from scratch with the required resources is more on the order of tens to hundreds of thousands of dollars rather than $400.
True, but $400 is probably not far low.
I must hasten to add that high density FPGAs have many many legitimate uses in prototyping logic and producing products in small volumes too small to justify the tooling costs of doing mask programmed gate arrays (which tend to be significantly faster and easier to design, but cost $5-100K NRE to set up custom masks for fabrication). The current generation of them make it possible to build logic systems in one small chip that a few years ago would have been large PC boards full of PALs and other logic.
My employer uses FPGAs in all new designs for production. They are *very* common for products that sell into the thousands per year. Mask-programmed gate arrays have the major disadvantage of very long lead times, usually a more pressing requirement than saving $30 per board over several thousand boards. Companies now make boards that contain just FPGAs wired in a grid. They are sold as general-purpose logic engines with software to implement circuits as hardware simulations. I'm sure that these would do just fine, though they are costly. ------------------------------------------------------------------------- Steven Weller | Weller's three steps to Greatness: | 1. See what others cannot | 2. Think what others cannot stevenw@best.com | 3. Express what others cannot